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High Voltage, Low Noise, Low Distortion, Unity Gain Stable, High Speed Op Amp ADA4898-1
FEATURES
Ultralow noise 0.9 nV/Hz 2.4 pA/Hz 1.2 nV/Hz @10 Hz Ultralow distortion: -93 dBc at 500 kHz Wide supply voltage range: 5 V to 16 V High speed -3 dB bandwidth: 65 MHz (G = +1) Slew rate: 55 V/s Unity gain stable Low input offset voltage: 150 V maximum Low input offset voltage drift: 1 V/C Low input bias current: -0.1 A Low input bias current drift: 2 nA/C Supply current: 8 mA Power-down feature
CONNECTION DIAGRAM
ADA4898-1
NC 1 -IN 2 +IN 3 -VS 4
8 7 6 5
PD +VS OUT
07037-001
NC
NC = NO CONNECT
Figure 1. 8-Lead SOIC_N_EP (RD-8)
APPLICATIONS
Instrumentation Active filters DAC buffers SAR ADC drivers Optoelectronics
GENERAL DESCRIPTION
The ADA4898-1 is an ultralow noise and distortion, unity gain stable, voltage feedback op amp that is ideal for use in 16-bit and 18-bit systems with power supplies from 5 V to 16 V. The ADA4898-1 features a linear, low noise input stage and internal compensation that achieves high slew rates and low noise. With the wide supply voltage range, low offset voltage, and wide bandwidth, the ADA4898-1 is designed to work in the most demanding applications. The ADA4898-1 also features an input bias current cancellation mode that reduces input bias current by a factor of 60. The ADA4898-1 is available in an 8-lead SOIC package that features an exposed metal paddle on its underside that improves heat transfer to the ground plane. This is a significant improvement over traditional plastic packages. The ADA4898-1 is rated to work over the extended automotive temperature range of -40C to +105C.
10 10
CURRENT
VOLTAGE NOISE (nV/Hz)
1
VOLTAGE
1
FREQUENCY (Hz)
Figure 2. Input Voltage Noise and Current Noise vs. Frequency
Rev. 0
Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 www.analog.com Fax: 781.461.3113 (c)2008 Analog Devices, Inc. All rights reserved.
07037-002
0.1
1
10
100
1k
10k
0.1 100k
CURRENT NOISE (pA/Hz)
ADA4898-1 TABLE OF CONTENTS
Features .............................................................................................. 1 Applications....................................................................................... 1 Connection Diagram ....................................................................... 1 General Description ......................................................................... 1 Revision History ............................................................................... 2 Specifications with 15 V Supply................................................... 3 Specifications with 5 V Supply ..................................................... 4 Absolute Maximum Ratings............................................................ 5 Thermal Resistance ...................................................................... 5 Maximum Power Dissipation ..................................................... 5 ESD Caution.................................................................................. 5 Pin Configuration and Function Descriptions............................. 6 Typical Performance Characteristics ............................................. 7 Test Circuits..................................................................................... 12 Theory of Operation ...................................................................... 13 PD (Power Down) Pin............................................................... 13 Current Noise Measurement .................................................... 13 Applications Information .............................................................. 14 Higher Feedback Gain Operation............................................ 14 Recommended Values for Various Gains................................ 14 Noise ............................................................................................ 15 Circuit Considerations .............................................................. 15 PCB Layout ................................................................................. 15 Power Supply Bypassing ............................................................ 15 Grounding ................................................................................... 15 Outline Dimensions ....................................................................... 16 Ordering Guide .......................................................................... 16
REVISION HISTORY
5/08--Revision 0: Initial Release
Rev. 0 | Page 2 of 16
ADA4898-1 SPECIFICATIONS WITH 15 V SUPPLY
TA = 25C, G = +1, RF = 0 , RG open, RL = 1 k to GND (for G > 1, RF = 100 ), unless otherwise noted. Table 1.
Parameter DYNAMIC PERFORMANCE -3 dB Bandwidth Bandwidth for 0.1 dB Flatness Slew Rate Settling Time to 0.1% NOISE/DISTORTION PERFORMANCE Harmonic Distortion SFDR Conditions VOUT = 100 mV p-p VOUT = 2 V p-p G = +2, VOUT = 2 V p-p VOUT = 5 V step VOUT = 5 V step f = 100 kHz, VOUT = 2 V p-p f = 500 kHz, VOUT = 2 V p-p f = 1 MHz, VOUT = 2 V p-p f = 100 kHz f = 100 kHz Min Typ 65 14 3.3 55 85 -116 -93 -79 0.9 2.4 20 1 -0.1 0.03 2 103 5 30 0.8 2.2 11 -126 -14 -13 -0.1 -0.2 -11.4 to +12.1 12.76 -11.7 to +12.2 12.82 150 80 16.5 8.1 0.1 -107 -114 110 -0.4 0.3 Max Unit MHz MHz MHz V/s ns dBc dBc dBc nV/Hz pA/Hz V V/C A A nA/C dB k M pF pF V dB V V A A V V mA dB V mA mA dB dB
Input Voltage Noise Input Current Noise DC PERFORMANCE Input Offset Voltage Input Offset Voltage Drift Input Bias Current Input Bias Offset Current Input Bias Current Drift Open-Loop Gain INPUT CHARACTERISTICS Input Resistance Input Capacitance Input Common-Mode Voltage Range Common-Mode Rejection Ratio PD (Power Down) PIN PD Input Voltages Input Leakage Current OUTPUT CHARACTERISTICS Output Voltage Swing Short-Circuit Current Off Isolation POWER SUPPLY Operating Range Quiescent Current Positive Power Supply Rejection Ratio Negative Power Supply Rejection Ratio
VOUT = 5 V Differential mode Common mode Differential mode Common mode VCM = 2 V Chip powered down Chip enabled PD = +VS PD = -VS RL = 1 k RL = None Sinking/sourcing f = 1 MHz, PD = -VS
99
-103
4.5 PD = +VS PD = -VS +VS = 15 V to 17 V, -VS = -15 V +VS = 15 V, -VS = -15 V to -17 V
-98 -100
Rev. 0 | Page 3 of 16
ADA4898-1 SPECIFICATIONS WITH 5 V SUPPLY
TA = 25C, G = +1, RF = 0 , RG open, RL = 1 k to GND (for G > 1, RF = 100 ), unless otherwise noted. Table 2.
Parameter DYNAMIC PERFORMANCE -3 dB Bandwidth Bandwidth for 0.1 dB Flatness Slew Rate Settling Time to 0.1% NOISE/DISTORTION PERFORMANCE Harmonic Distortion SFDR Input Voltage Noise Input Current Noise DC PERFORMANCE Input Offset Voltage Input Offset Voltage Drift Input Bias Current Input Bias Offset Current Input Bias Current Drift Open-Loop Gain INPUT CHARACTERISTICS Input Resistance Input Capacitance Input Common-Mode Voltage Range Common-Mode Rejection Ratio PD (Power Down) PIN PD Input Voltages Input Leakage Current OUTPUT CHARACTERISTICS Output Voltage Swing Short-Circuit Current Off Isolation POWER SUPPLY Operating Range Quiescent Current Positive Power Supply Rejection Ratio Negative Power Supply Rejection Ratio Conditions VOUT = 100 mV p-p VOUT = 2 V p-p G = +2, VOUT = 2 V p-p VOUT = 2 V step VOUT = 2 V step f = 500 kHz, VOUT = 2 V p-p f = 1 MHz, VOUT = 2 V p-p f = 100 kHz f = 100 kHz Min Typ 57 12 3 50 90 -95 -78 0.9 2.4 30 1 -0.1 0.01 2 94 5 30 0.8 2.2 -3 to +2.5 -120 -4 -3 0.1 -2 3.12 3.3 3.17 3.34 150 80 16.5 7.7 0.1 -100 -104 150 -0.4 0.3 Max Unit MHz MHz MHz V/s ns dBc dBc nV/Hz pA/Hz V V/C A A nA/C dB k M pF pF V dB V V A A V V mA dB V mA mA dB dB
VOUT = 1 V Differential mode Common mode Differential mode Common mode VCM = 1 V Chip powered down Chip enabled PD = +VS PD = -VS RL = 1 k RL = None Sinking/sourcing f = 1 MHz, PD = -VS
90
-102
4.5 PD = +VS PD = -VS +VS = 5 V to 7 V, -VS = -5 V +VS = 5 V, -VS = -5 V to -7 V
-95 -97
Rev. 0 | Page 4 of 16
ADA4898-1 ABSOLUTE MAXIMUM RATINGS
Table 3.
Parameter Supply Voltage Power Dissipation Differential Mode Input Voltage Common-Mode Input Voltage Storage Temperature Range Operating Temperature Range Lead Temperature (Soldering, 10 sec) Junction Temperature Rating 36 V See Figure 3 1.5 V 11.4 V -65C to +150C -40C to +105C 300C 150C
The power dissipated in the package (PD) is the sum of the quiescent power dissipation and the power dissipated in the package due to the output load drive. The quiescent power is the voltage between the supply pins (VS) times the quiescent current (IS). The power dissipated due to the load drive depends upon the particular application. For each output, the power due to load drive is calculated by multiplying the load current by the associated voltage drop across the device. RMS voltages and currents must be used in these calculations. Airflow increases heat dissipation, effectively reducing JA. In addition, more metal directly in contact with the package leads from metal traces, through holes, ground, and power planes reduces the JA. The exposed paddle on the underside of the package must be soldered to a pad on the PCB surface that is thermally connected to a copper plane to achieve the specified JA. Figure 3 shows the maximum safe power dissipation in the package vs. the ambient temperature for the 8-lead SOIC_EP (47C/W) on a JEDEC standard four-layer board, with its underside paddle soldered to a pad that is thermally connected to a PCB plane. JA values are approximations.
4.5 4.0
Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
THERMAL RESISTANCE
JA is specified for the worst-case conditions, that is, JA is specified for a device soldered in the circuit board with its exposed paddle soldered to a pad on the PCB surface that is thermally connected to a copper plane, with zero airflow. Table 4.
Package Type 8-Lead SOIC with EP on Four-Layer Board JA 47 JC 29 Unit C/W
MAXIMUM POWER DISSIPATION (W)
3.5 3.0 2.5 2.0 1.5 1.0 0.5 10 20 30 40 50 60 70 80 90 100
07037-003
MAXIMUM POWER DISSIPATION
The maximum safe power dissipation in the ADA4898-1 package is limited by the associated rise in junction temperature (TJ) on the die. At approximately 150C, which is the glass transition temperature, the plastic changes its properties. Even temporarily exceeding this temperature limit can change the stresses that the package exerts on the die, permanently shifting the parametric performance of the ADA4898-1. Exceeding a junction temperature of 150C for an extended period can result in changes in the silicon devices, potentially causing failure.
0 -40 -30 -20 -10 0
AMBIENT TEMPERATURE (C)
Figure 3. Maximum Power Dissipation vs. Ambient Temperature
ESD CAUTION
Rev. 0 | Page 5 of 16
ADA4898-1 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
NC 1 -IN 2
7 +VS TOP VIEW +IN 3 (Not to Scale) 6 OUT
07037-046
ADA4898-1
8
PD
-VS 4
5
NC
NC = NO CONNECT
Figure 4. Pin Configuration
Table 5. Pin Function Descriptions
Pin No. 1 2 3 4 5 6 7 8 Mnemonic NC -IN +IN -VS NC OUT +VS PD Description No Connect Inverting Input Noninverting Input Negative Supply No Connect Output Positive Supply Power Down
Rev. 0 | Page 6 of 16
ADA4898-1 TYPICAL PERFORMANCE CHARACTERISTICS
3 2 3 2
NORMALIZED CLOSED-LOOP GAIN (dB)
NORMALIZED CLOSED-LOOP GAIN (dB)
G = +1 RF = 100
1 0 -1 -2 -3 -4 -5 -6 -7 -8 -9 -10 -11 -12 1 RL = 1k VOUT = 100mV p-p VS = 15V 10 FREQUENCY (MHz) G = +2 RF = 100 G = +5 RF = 100
G = +1 RF = 0
1 0 -1 -2 -3 -4 -5 -6 -7 -8 -9 -10 -11 -12 RL = 1k VOUT = 2V p-p VS = 15V
G = +1 RF = 0
G = +1 RF = 100
G = +2 RF = 100
G = +5 RF = 100
100
07037-004
FREQUENCY (MHz)
Figure 5. Small Signal Frequency Response for Various Gains
3 2 1 0 RL = 1k
Figure 8. Large Signal Frequency Response for Various Gains
1 0 -1 RL = 1k
CLOSED-LOOP GAIN (dB)
CLOSED-LOOP GAIN (dB)
-1 -2 -3 -4 -5 -6 -7 -8 -9 -10 -11 -12 1 G = +1 VOUT = 100mV p-p VS = 15V 10 FREQUENCY (MHz) 100
07037-005
-2 -3 -4 -5 -6 -7 -8 -9 -10 -11 -12 1 G = +1 VOUT = 2V p-p VS = 15V 10 FREQUENCY (MHz) 100
07037-008 07037-009
RL = 100 RL = 200
RL = 100
RL = 200
Figure 6. Small Signal Frequency Response for Various Loads
2 1 0 -1
Figure 9. Large Signal Frequency Response for Various Loads
2 1 0 -1
T = +105C
T = +85C
T = +105C T = +85C
CLOSED-LOOP GAIN (dB)
CLOSED-LOOP GAIN (dB)
-2 -3 -4 -5 -6 -7 -8 -9 -10 -11 -12 1 G = +1 RL = 1k VOUT = 100mV p-p VS = 15V
-2 -3 -4 -5 -6 -7 -8 -9 -10 -11 -12 G = +1 RL = 1k VOUT = 2V p-p VS = 15V 1 10 T = -40C T = 0C
T = +25C T = 0C T = -40C
T = +25C
07037-006
10 FREQUENCY (MHz)
100
100
FREQUENCY (MHz)
Figure 7. Small Signal Frequency Response for Various Temperatures
Figure 10. Large Signal Frequency Response for Various Temperatures
Rev. 0 | Page 7 of 16
07037-007
1
10
100
ADA4898-1
2 1 0 -1 VS = 15V 2 1 0 -1
CLOSED-LOOP GAIN (dB)
-2 -3 -4 -5 -6 -7 -8 -9 -10 -11 -12 1 G = +1 RL = 1k VOUT = 100mV p-p
07037-010
CLOSED-LOOP GAIN (dB)
-2 -3 -4 -5 -6 -7 -8 -9 -10 -11 -12 G = +1 RL = 1k VOUT = 2V p-p 1 10 VS = 5V
VS = 15V
VS = 5V
10 FREQUENCY (MHz)
100
100
FREQUENCY (MHz)
Figure 11. Small Signal Frequency Response for Various Supply Voltages
3 2 1 0 CL = 5pF
Figure 14. Large Signal Frequency Response for Various Supply Voltages
1.0 0.9 0.8 0.7
CLOSED-LOOP GAIN (dB)
-2 -3 -4 -5 -6 -7 -8 -9 -10 -11 -12 1 G = +1 RL = 1k VOUT = 100mV p-p VS = 15V 10
NORMALIZED GAIN (dB)
-1
CL = 0pF
0.6 0.5 0.4 0.3 0.2 0.1 0 -0.1 -0.2 -0.3 -0.4 G = +2 RL = 1k VS = 15V 1M FREQUENCY (Hz) 10M
07037-014 07037-035
CL = 33pF
VOUT = 0.1V p-p
CL = 15pF
VOUT = 2V p-p
100
FREQUENCY (MHz)
Figure 12. Small Signal Frequency Response for Various Capacitive Loads
10 100
07037-011
-0.5 100k
Figure 15. 0.1 dB Flatness for Various Output Voltages
VOLTAGE NOISE (nV/Hz)
1
CURRENT NOISE (pA/Hz)
10
1
10
100
1k
10k
100k
07037-012
0.1
1
1
10
100
1k
10k
100k
FREQUENCY (Hz)
FREQUENCY (Hz)
Figure 13. Voltage Noise vs. Frequency
Figure 16. Input Current Noise vs. Frequency
Rev. 0 | Page 8 of 16
07037-013
ADA4898-1
110 100 90 80 PHASE -70 -80 -90 -100 -95
f = 100kHz G = +1 RL = 1k VS = 15V
DISTORTION (dBc)
70 60 50 40 30 20 10 0 -10 -20 100k 1M 10M FREQUENCY (Hz) 100M GAIN
-110 -120 -130 -140 -150 -160 -170 -180 -190
OPEN-LOOP PHASE (Degrees)
-100
OPEN-LOOP GAIN (dB)
-105 -110
HD2
-115 -120 -125
HD3
-130 -135
07037-016
1
2
3
4
5
6
OUTPUT VOLTAGE (V p-p)
Figure 17. Open-Loop Gain and Phase vs. Frequency
0
0
Figure 20. Harmonic Distortion vs. Output Amplitude
RL = 1k VS = 15V -20 VOUT = 2V p-p -40
G = +2, HD3, RF = 250
-20 -40
G = +1 VS = 5V VOUT = 2V p-p
RL = 100, HD3
DISTORTION (dBc)
DISTORTION (dBc)
G = +2, HD2, RF = 250 -60 -80 G = +1, HD3 -100 -120 -140 100k G = +1, HD2
RL = 100, HD2 -60 -80 -100 RL = 1k, HD2 -120 -140 100k
RL = 1k, HD3
07037-017
1M FREQUENCY (Hz)
10M
1M FREQUENCY (Hz)
10M
Figure 18. Harmonic Distortion vs. Frequency and Gain
Figure 21. Harmonic Distortion vs. Frequency and Loads
0 -20 -40
G = +1 VS = 15V VOUT = 2V p-p
0.14
RL = 100, HD3
VOUT = 100mV p-p G = +1 0.12 R = 1k L VS = 15V 0.10
OUTPUT VOLTAGE (V)
CL = 15pF
DISTORTION (dBc)
0.08 0.06 0.04 0.02 0
CL = 0pF
-60 -80 -100
RL = 100, HD2
CL = 5pF
RL = 1k, HD3 -120 RL = 1k, HD2 1M FREQUENCY (Hz) 10M
07037-018
-0.02 -0.04
-140 100k
TIME (20ns/DIV)
Figure 19. Harmonic Distortion vs. Frequency and Loads
Figure 22. Small Signal Transient Response for Various Capacitive Loads
Rev. 0 | Page 9 of 16
07037-021
CL = 33pF
07037-020
07073-019
-200 1G
ADA4898-1
0.14 VOUT = 100mV p-p RL=1k 0.12 V = 15V S 0.10
OUTPUT VOLTAGE (V) 2.5
G = +1
2.0 OUTPUT VOLTAGE (V)
VOUT = 2V p-p G = +1 RL= 1k
0.08 0.06 0.04 0.02 0
G = +2
1.5 VS = 5V 1.0
0.5 VS = 15V
0
-0.02
07037-022
-0.04
TIME (20ns/DIV)
-0.5
TIME (100ns/DIV)
Figure 23. Small Signal Transient Response for Various Gains
2.5 2.5
Figure 26. Large Signal Transient Response for Various Supply Voltages, RL = 1 k
VOUT = 2V p-p RL = 1k VS = 15V
2.0
OUTPUT VOLTAGE (V)
VOUT = 2V p-p G = +1 RL = 100
2.0
OUTPUT VOLTAGE (V)
1.5
VS = 5V
1.5 G = +2 1.0
1.0
0.5 VS = 15V
0.5 G = +1 0
0
07037-023
-0.5
-0.5
TIME (100ns/DIV)
TIME (100ns/DIV)
Figure 24. Large Signal Transient Response for Various Supply Voltages, RL = 100
0.5 0.4 0.3 INPUT t = 85ns OUTPUT G = +1 RL = 1k VOUT = 5V p-p VS = 15V
Figure 27. Large Signal Transient Response for Various Gains
90 80 70 VOUT = 0.1V p-p DISABLED
OUTPUT IMPEDANCE (dB)
SETTLING TIME (%)
0.2 0.1 0 0.1 0.2 0.3 0.4 0.5
60 50 40 30 20 10 0 -10 VOUT = 0.1V p-p ENABLED G = +1 RF = 0 RL = 0 VS = 15V 100M 1G
07037-028
VOUT = 2V p-p ENABLED VOUT = 2V p-p DISABLED
07037-026
TIMES (10ns/DIV)
-20 100k
1M
10M FREQUENCY (Hz)
Figure 25. Settling Time
Figure 28. Output Impedance vs. Frequency
Rev. 0 | Page 10 of 16
07037-024
07037-025
ADA4898-1
0 -20 -40
-40 0
-20
CMRR (dB)
-60 -80 -100 -120 -140 100 G = +1 RL = 100 VS = 15V VOUT = 2V p-p
07037-029
PSRR (dB)
-60
-80
+PSRR
-100
-PSRR
1k
10k
100k
1M
10M
100M
100k FREQUENCY (Hz)
1M
10M
FREQUENCY (Hz)
Figure 29. Common-Mode Rejection Ratio (CMRR) vs. Frequency
Figure 32. Power Supply Rejection Ratio (PSRR) vs. Frequency
-45
1000
N = 6180 MEAN: -0.13 SD: 0.02 VS = 15V
VOUT = 0.1V p-p
800
PD ISOLATION (dB)
-55
COUNT
600
VOUT = 2V p-p
400
-65
200
INPUT BIAS CURRENT (A)
FREQUENCY (Hz)
Figure 30. Input Bias Current Distribution
1000 N = 6180 MEAN: 27 SD: 20 VS = 15V
1000
Figure 33. PD Isolation vs. Frequency
800
N = 6180 MEAN: -2.8 SD: 20 VS = 5V
800
600
COUNT
400
COUNT
600
400
200
200
-90
-60
-30
0
30
60
90
OFFSET VOLTAGE (V)
OFFSET VOLTAGE (V)
Figure 31. Input Offset Voltage Distribution, VS = 15 V
Figure 34. Input Offset Voltage Distribution, VS = 5 V
Rev. 0 | Page 11 of 16
07037-034
-30
0
30
60
90
120
07037-033
0 -60
0
07037-031
-0.20
-0.15
-0.10
-0.05
0
07037-032
0 -0.25
-75 100k
G = +1 RL = 1k VS = 15V 1M 10M 100M
07037-030
-120 10k
G = +1 RL = 100 VS = 15V VOUT = 2V p-p
ADA4898-1 TEST CIRCUITS
+VS 10F
+VS 10F
+
+
0.1F VIN 49.9 10F 0.1F VOUT RL
RG
RF 0.1F 0.1F VOUT 49.9 CL RL
VIN
07037-036
+
0.1F -VS
10F
+
07037-039
0.1F -VS
Figure 35. Typical Noninverting Load Configuration
+VS
Figure 38. Typical Capacitive Load Configuration
+VS 10F
AC
49.9
+
0.1F
VOUT RL
VOUT RL 49.9 AC
10F
07037-037
-VS
-VS
Figure 36. Positive Power Supply Rejection
+VS 10F
+
Figure 39. Negative Power Supply Rejection
1k 1k VIN 1k 53.6 1k 10F
+
07037-038
0.1F
0.1F VOUT RL
0.1F -VS
Figure 37. Common-Mode Rejection
Rev. 0 | Page 12 of 16
07037-040
0.1F
+
ADA4898-1 THEORY OF OPERATION
The ADA4898-1 is a voltage feedback op amp that combines unity-gain stability with 0.9 nV/Hz input noise. It employs a highly linear input stage that can maintain greater than -90 dBc (@ 2 V p-p) distortion out to 500 kHz while in a unity-gain configuration. This rare combination of low gain stability, low input referred noise, and extremely low distortion is the result of Analog Devices, Inc., proprietary op amp architecture and high speed complementary bipolar processing technology. The simplified ADA4898-1 topology, shown in Figure 40, is a single gain stage with a unity-gain output buffer. It has over 100 dB of open-loop gain and maintains precision specifications such as CMRR, PSRR and offset to levels that are normally associated with topologies having two or more gain stages.
CURRENT NOISE MEASUREMENT
To measure the very low (2.4 pA/Hz) input current noise of the ADA4898-1, 10 k resistors were used on both inputs of the amplifier. Figure 41 shows the noise measurement circuit used. The 10 k resistors are used on both inputs to balance the input impedance and cancel the common-mode noise. In addition, a high gain configuration is used to increase the total output noise and bring it above the noise floor of the instrument.
10 100 10k
07037-042
10k
VOUT
Figure 41. Current Noise Measurement Circuit
R1
CC
RL
07037-041
gm
BUFFER
VOUT
The current noise density (In) is calculated using the following formula:
Figure 40. Topology
In =
[e
2 no
- (11 x 18.4 nV/ Hz )2 20 k x 11
]
1/ 2
x2
PD (POWER DOWN) PIN
The PD pin saves power by decreasing the quiescent power dissipated in the device. It is very useful when power is an issue and the device does not need to be turned on at all times. The response of the device is rapid when going from a power down mode to full power operation mode. Note that PD does not put the output in a high-Z state, which means that the ADA4898-1 is not recommended for use as a multiplexer.
Rev. 0 | Page 13 of 16
ADA4898-1 APPLICATIONS INFORMATION
HIGHER FEEDBACK GAIN OPERATION
The ADA4898-1 schematic for the noninverting gain configuration is nearly a textbook example (see Figure 42). The only exception is the feedback capacitor in parallel with the feedback resistor, RF, but this capacitor is recommended only when using a large RF value (>300 ). Figure 43 shows the difference between using a 100 resistor and a 1 k resistor. Due to the high input capacitance in the ADA4898-1 when using a higher feedback resistor, more peaking appears in the closed-loop gain. Using the lower feedback resistor resolves this issue; however, when running at higher supplies (15 V) with 100 RF, the system draws a lot of extra current into the feedback network. To avoid this problem, a higher feedback resistor can be used with a feedback capacitor in parallel. Figure 43 shows the effect of placing a feedback capacitor in parallel with a larger RF. In this gain of 2 configuration, RF = RG = 1 k and CF = 2.7 pF. When using CF, the peaking drops from 6 dB to less then 2 dB.
CF
12 G = +2 RL = 1k 9 VS = 15V 6 3 0 -3 -6 -9 -12 1M 10M FREQUENCY (Hz) 100M
07037-044
RF = 1k RF = 100 RF = 1k, CF = 2.7pF
CLOSED-LOOP GAIN (dB)
-15 100k
Figure 43. Small Signal Frequency Response for Various Feedback Impedances
RECOMMENDED VALUES FOR VARIOUS GAINS
Table 6 provides a useful reference for determining various gains and associated performance. Resistor RF is set to 100 for gains greater than 1. A low feedback RF resistor value reduces peaking and minimizes the contribution to the overall noise performance of the amplifier.
RF
RF
+VS
10F
+
0.1F
0.1F VOUT
VIN
RL RT 10F
+
-VS
Figure 42. Noninverting Gain Schematic
Table 6. Various Gains and Recommended Resistor Values Associated (Conditions: VS = 5 V, TA = 25C, RL = 1 k, RT = 49.9 )
Gain +1 +2 +5 RF () 0 100 100 RG () NA 100 24.9 -3 dB SS BW (MHz), VOUT = 100 mV p-p 65 30 9 Slew Rate (V/s), VOUT = 2 V Step 55 50 45 ADA4898-1 Voltage Noise (nV/Hz), RTO 0.9 1.8 4.5 Total System Noise (nV/Hz), RTO 1.29 3.16 7.07
07037-043
0.1F
Rev. 0 | Page 14 of 16
ADA4898-1
NOISE
To analyze the noise performance of an amplifier circuit, identify the noise sources, and then determine if each source has a significant contribution to the overall noise performance of the amplifier. To simplify the noise calculations, noise spectral densities were used rather than actual voltages to leave bandwidth out of the expressions (noise spectral density, which is generally expressed in nV/Hz, is equivalent to the noise in a 1 Hz bandwidth). The noise model shown in Figure 44 has six individual noise sources: the Johnson noise of the three resistors, the op amp voltage noise, and the current noise in each input of the amplifier. Each noise source has its own contribution to the noise at the output. Noise is generally specified referred to input (RTI), but it is often simpler to calculate the noise referred to the output (RTO) and then divide by the noise gain to obtain the RTI noise.
VN, R2 4kTR2 B VN, R1 4kTR1 VN, R3 4kTR3 R1 IN- VN R3 IN+ R2 GAIN FROM = A TO OUTPUT NOISE GAIN = NG = 1 + R2 R1 VOUT GAIN FROM = - R2 B TO OUTPUT R1
CIRCUIT CONSIDERATIONS
Careful and deliberate attention to detail when laying out the ADA4898-1 board yields optimal performance. Power supply bypassing, parasitic capacitance, and component selection all contribute to the overall performance of the amplifier.
PCB LAYOUT
Because the ADA4898-1 can operate up to 65 MHz, it is essential that RF board layout techniques be employed. All ground and power planes under the pins of the ADA4898-1 should be cleared of copper to prevent the formation of parasitic capacitance between the input pins to ground and the output pins to ground. A single mounting pad on a SOIC footprint can add as much as 0.2 pF of capacitance to ground if the ground plane is not cleared from under the mounting pads.
POWER SUPPLY BYPASSING
Power supply bypassing for the ADA4898-1 has been optimized for frequency response and distortion performance. Figure 42 shows the recommended values and location of the bypass capacitors. Power supply bypassing is critical for stability, frequency response, distortion, and PSR performance. The 0.1 F capacitors shown in Figure 42 should be as close to the supply pins of the ADA4898-1 as possible. The 10 F electrolytic capacitors should be adjacent to but not necessary close to the 0.1 F capacitors. The capacitor between the two supplies helps improve PSR and distortion performance. In some cases, additional paralleled capacitors can help improve frequency and transient response.
A
VN2 + 4kTR3 + 4kTR1 RTI NOISE =
R2 R1 + R2
2
2
07037-045
+ IN+2R32 + IN-2 R1 x R2 R1 + R2
+ 4kTR2
R1 R1 + R2
2
GROUNDING
Ground and power planes should be used where possible. Ground and power planes reduce the resistance and inductance of the power planes and ground returns. The returns for the input and output terminations, bypass capacitors, and RG should all be kept as close to the ADA4898-1 as possible. The output load ground and the bypass capacitor grounds should be returned to the same point on the ground plane to minimize parasitic trace inductance, ringing, and overshoot and to improve distortion performance. The ADA4898-1 package features an exposed paddle. For optimum electrical and thermal performance, solder this paddle to ground. For more information on high speed circuit design, see A Practical Guide to High-Speed Printed-Circuit-Board Layout at www.analog.com.
RTO NOISE = NG x RTI NOISE
Figure 44. Op Amp Noise Analysis Model
All resistors have a Johnson noise that is calculated by
(4kBTR) .
where: k is Boltzmann's Constant (1.38 x 10-23 J/K). B is the bandwidth in Hertz. T is the absolute temperature in Kelvin. R is the resistance in ohms. A simple relationship that is easy to remember is that a 50 resistor generates a Johnson noise of 1 nV/Hz at 25C. In applications where noise sensitivity is critical, care must be taken not to introduce other significant noise sources to the amplifier. Each resistor is a noise source. Attention to the following areas is critical to maintain low noise performance: design, layout, and component selection. A summary of noise performance for the amplifier and associated resistors can be seen in Table 6.
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ADA4898-1 OUTLINE DIMENSIONS
4.00 (0.157) 3.90 (0.154) 3.80 (0.150) 5.00 (0.197) 4.90 (0.193) 4.80 (0.189)
8 1 5 4
2.29 (0.090)
TOP VIEW
6.20 (0.244) 6.00 (0.236) 5.80 (0.228) BOTTOM VIEW
(PINS UP)
2.29 (0.090)
1.27 (0.05) BSC 1.75 (0.069) 1.35 (0.053) 0.10 (0.004) MAX COPLANARITY 0.10 1.65 (0.065) 1.25 (0.049) SEATING PLANE
0.50 (0.020) 0.25 (0.010)
45
0.51 (0.020) 0.31 (0.012)
0.25 (0.0098) 0.17 (0.0067)
8 0
1.27 (0.050) 0.40 (0.016)
COMPLIANT TO JEDEC STANDARDS MS-012-A A
060506A
CONTROLLING DIMENSIONS ARE IN MILLIMETER; INCH DIMENSIONS (IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN.
Figure 45. 8-Lead Standard Small Outline Package with Exposed Pad [SOIC_N_EP] (RD-8-1) Dimensions shown in millimeters and (inches)
ORDERING GUIDE
Model ADA4898-1YRDZ 1 ADA4898-1YRDZ-R71 ADA4898-1YRDZ-RL1
1
Temperature Range -40C to +105C -40C to +105C -40C to +105C
Package Description 8-Lead SOIC_N_EP 8-Lead SOIC_N_EP 8-Lead SOIC_N_EP
Package Option RD-8-1 RD-8-1 RD-8-1
Ordering Quantity 1 1,000 2,500
Z = RoHS Compliant Part.
(c)2008 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D07037-0-5/08(0)
Rev. 0 | Page 16 of 16

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